HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 188

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
188 of 272
R_SL_SEL6
Slot selection register for pin F1_6
This multi-register is selected with bitmap V_PCM_ADDR = 6 of the register
R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_6 is disabled.
6..0
7
R_SL_SEL7
Slot selection register for pin F1_7
This multi-register is selected with bitmap V_PCM_ADDR = 7 of the register
R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_7 is disabled.
6..0
7
Bits
Bits
0x7F
0x7F
1
1
Reset
Value
Reset
Value
Name
V_SL_SEL6
V_SH_SEL6
Name
V_SL_SEL7
V_SH_SEL7
PCM interface
(write only)
(write only)
Data Sheet
PCM time slot selection
PCM time slot selection
Description
The selected slot number is V_SL_SEL1 ·½ for
F1_6. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Shape selection
’0’ = use shape 1 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
Description
The selected slot number is V_SL_SEL1 ·½ for
F1_7. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
March 2003 (rev. A)
Cologne
Chip
0x15
0x15