HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 117

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

channel during the first 125 s cycle. During the next 125 s cycle the next
same byte are processed, and so on. When 8 FIFO bits are processed, the next FIFO byte is
processed. The byte boundaries are neglected.
Simple Mode
HDLC mode combined with Simple Mode can transmit one FIFO bit stream (e.g. of FIFO[
to the connected HFC-channel. The result is given in Table 3.7
Received HFC-channel data are processed similar. FIFO[
stores 3 bits every 125 s cycle. These bits are taken from the connected HFC-channel at
position [4 . . . 2].
Channel Select Mode
In Channel Select Mode several FIFOs can transmit a bit stream to one connected HFC-
channel. Figure 3.11 with three connected FIFOs to HFC-channel[ ,TX] is taken again as
an example. HFC-channel transmit data for this configuration is shown in Table 3.8
Received HFC-channel data are processed similary. Assuming that three receive FIFOs are
configured with the same settings as their corresponding transmit FIFOs, then FIFO[
receives a bit stream with 3 kByte/s, FIFO[
ceives 1 kByte/s.
March 2003 (rev. A)
HFC-E1
10
9
HDLC bit stuffing is not shown in this example.
HDLC bit stuffing is not shown in this example.
Table 3.7: Subchannel processing example in SM combined with HDLC mode (transmit direction)
channel mask:
HFC-channel transmit byte 1:
HFC-channel transmit byte 2:
HFC-channel transmit byte 3:
HFC-channel transmit byte 4:
A_SUBCH_CFG[m,RX] : V_BIT_CNT
. . .
: V_START_BIT
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Data Sheet
Data flow
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,RX] receives 2 kByte/s and FIFO[
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Cologne
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