AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1003

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6438F–ATARM–21-Jun-10
• When destination peripheral is defined as the flow controller, if the destination width is
• When a Memory to Peripheral transfer occurs if the destination peripheral is flow controller,
• You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte,
• After the software disables a channel by writing into the channel disable register, it must re-
• If you program the BTSIZE field in the DMAC_CTRLA, as zero, and the DMAC is defined as
• When hardware handshaking interface protocol is fully implemented, a peripheral is expected
• Multiple Transfers involving the same peripheral must not be programmed and enabled on
• When a Peripheral is flow controller, the targeted DMAC Channel must be enabled before the
• When AUTO Field is set to TRUE, then the BTSIZE Field is automatically reloaded from its
smaller than the source width, then a data loss may occur, and the loss is equal to Source
Single Transfer size in bytes- destination Single Transfer size in bytes.
then a prefetch operation is performed. It means that data are extracted from memory before
any request from the peripheral is generated.
half-word and word aligned address depending on the source width and destination width.
enable the channel only after it has polled a 0 in the corresponding channel enable status
register. This is because the current AHB Burst must terminate properly.
the flow controller, then the channel is automatically disabled.
to deassert any sreq or breq signals on receiving the ack signal irrespective of the request
the ack was asserted in response to.
different channel, unless this peripheral integrates several hardware handshaking interface.
Peripheral. If you do not ensure this the DMAC Channel might miss a Last Transfer Flag, if
the First DMAC request is also the last transfer.
previous value. BTSIZE must be initialized to a non zero value if the first transfer is initiated
with AUTO field set to TRUE even if LLI mode is enabled because the LLI fetch operation will
not update this field.
AT91SAM9G45
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