AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 830

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 38-3.
Notes:
38.5.4
Figure 38-4. Control Read and Write Sequences
38.5.5
830
CONTROL
(bidirectional)
OUT
(host toward device)
1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake.
2. Isochronous transfers must use endpoints configured with two or three banks.
AT91SAM9G45
USB V2.0 High Speed BUS Transactions
Endpoint Configuration
USB Transfer Events (Continued)
Control Write
Control Read
No Data
Control
Control Transfers
Bulk OUT Transfer
Interrupt OUT Transfer
Isochronous OUT Transfer
An endpoint handles all transactions related to the type of transfer for which it has been
configured.
Each transfer results in one or more transactions over the USB bus.
There are five kinds of transactions flowing across the bus in packets:
A status IN or OUT transaction is identical to a data IN or OUT transaction.
The endpoint 0 is always a control endpoint, it must be programmed and active in order to be
enabled when the End Of Reset interrupt occurs.
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
4. Status IN Transaction
5. Status OUT Transaction
Setup Stage
Setup Stage
Setup Stage
Setup TX
Setup TX
Setup TX
(1)
(2)
Status Stage
Status IN TX
Data OUT TX
Data IN TX
• Setup transaction
• Setup transaction
• Setup transaction
• Data OUT transaction
• Data OUT transaction
• Data OUT transaction
Data Stage
Data Stage
Data OUT TX
Data IN TX
Data IN transactions
Data OUT transactions
Status IN transaction
Data OUT transaction
Data OUT transaction
Data OUT transaction
Status OUT TX
Status Stage
Status Stage
Status IN TX
Status OUT transaction
Status IN transaction
6438F–ATARM–21-Jun-10