AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1036

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Note:
1036
Polarity and alignment can be modified only when the channel is disabled.
AT91SAM9G45
Figure 42-6. Synchronized Period or Duty Cycle Update
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to
synchronize his software. Two methods are possible. In both, the user must enable the dedi-
cated interrupt in PWM_IER at PWM Controller level.
The first method (polling method) consists of reading the relevant status bit in PWM_ISR Regis-
ter according to the enabled channel(s). See
The second method uses an Interrupt Service Routine associated with the PWM channel.
Note:
Figure 42-7. Polling Method
Reading the PWM_ISR register automatically clears CHIDx flags.
End of Cycle
Acknowledgement and clear previous register state
The last write has been taken into account
PWM_CPRDx
Update of the Period or Duty Cycle
Writing in PWM_CUPDx
PWM_CUPDx Value
Writing in CPD field
PWM_ISR Read
1
User's Writing
CHIDx = 1
Figure
YES
PWM_CDTYx
0
42-7.
PWM_CMRx. CPD
6438F–ATARM–21-Jun-10