AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 779

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6438F–ATARM–21-Jun-10
7. Poll CBTC[x] bit in the DMAC_EBCISR Register.
8. If a new list of buffers shall be transferred, repeat step 6. Check and handle HSMCI
9. Poll FIFOEMPTY field in the HSMCI_SR.
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMAC transfer by
c. Program a List of descriptors.
d. The LLI(n).DMAC_SADDRx memory location for channel x must be set to the loca-
e. The LLI(n).DMAC_DADDRx register for channel x must be set with the starting
f.
g. Program LLI(n).DMAC_CTRLBx register for channel x with the following field’s
h. Program LLI(n).DMAC_CFGx register for channel x with the following field’s values:
i.
j.
k. Program DMAC_DSCRx for channel register x with the address of the first descrip-
l.
errors.
reading the DMAC_EBCISR register.
tion of the source data. When the first data location is not word aligned, the two
LSB bits define the temporary value called dma_offset. The two LSB bits of
LLI(n).DMAC_SADDRx must be set to 0.
address of the HSMCI_FIFO address.
Program LLI(n).DMAC_CTRLAx register of channel x with the following field’s
values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with CEILING((block_length + dma_offset)/4).
values:
–DST_INCR is set to INCR.
–SRC_INCR is set to INCR.
–DST_DSCR is set to 0 (fetch operation is enabled for the destination).
–SRC_DSCR is set to 1 (source address is contiguous).
–FC field is programmed with memory to peripheral flow control mode.
–Both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_REP is set to 0. (contiguous memory access at block boundary)
–DST_PER is programmed with the hardware handshaking ID of the targeted
If LLI(n) is the last descriptor, then LLI(n).DSCR points to 0 else LLI(n) points to the
start address of LLI(n+1).
Program DMAC_CTRLBx for channel register x with 0. Its content is updated with
the LLI fetch operation.
tor LLI(0).
Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting
for request.
Controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
AT91SAM9G45
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