AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 17

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2.2
Table 6-1.
6.2.3
6.3
6.3.1
6.3.2
6438F–ATARM–21-Jun-10
seen at 0x100000 through AHB
SRAM A ITCM size (KBytes)
I/O Drive Selection and Delay Control
TCM Interface
Internal ROM
I/O Drive Selection
Delay Control
ITCM and DTCM Memory Configuration
32
0
0
On the processor side, this Internal SRAM can be allocated to two areas.
Within the 64Kbyte SRAM size available, the amount of memory assigned to each block is soft-
ware programmable according to
The AT91SAM9G45 embeds an Internal ROM, which contains the boot ROM and SAM-BA
program.
At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0
(BMS =1) after the reset and before the Remap Command.
The aim of this control is to adapt the signal drive to the frequency. Two bits allow the user to
select High or Low drive for memories data/address/ctrl signals.
To avoid the simultaneous switching of all the I/Os, a delay can be inserted on the different EBI,
DDR2 and PIO lines.
• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block
• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block
• Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap
• Setting the bit [17], EBI_DRIVE, in the EBI_CSA register of the matrix allows to control the
• Setting the bit [18], DDR_DRIVE, in the EBI_CSA register of the matrix allows to control the
anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR
configuration register located in the Chip Configuration User Interface. This SRAM block is
also accessible by the ARM926 Masters and by the AHB Masters through the AHB bus
anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus.
Command is performed, this SRAM block is accessible through the AHB bus at address
0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes
accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926
Data Masters.
drive of the EBI.
drive of the DDR.
seen at 0x200000 through AHB
SRAM B DTCM size (KBytes)
64
32
0
Table
6-1.
seen at 0x300000 through AHB
SRAM C (KBytes)
64
0
0
AT91SAM9G45
17
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