AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 275

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.7.12
Name:
Access:
Reset:
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x444452 (“DDR” in ASCII).
Protects the registers:
• WPKEY: Write Protect KEY
Should be written at value 0x444452 (“DDR” in ASCII). Writing any other value in this field aborts the write operation of the
WPEN bit. Always reads as 0.
6438F–ATARM–21-Jun-10
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“DDRSDRC Mode Register” on page 260
“DDRSDRC Refresh Timer Register” on page 261
“DDRSDRC Configuration Register” on page 262
“DDRSDRC Timing 0 Parameter Register” on page 265
“DDRSDRC Timing 1 Parameter Register” on page 267
“DDRSDRC Timing 2 Parameter Register” on page 268
“DDRSDRC Memory Device Register” on page 271
“DDRSDRC High Speed Register” on page 273
31
23
15
—
7
DDRSDRC Write Protect Mode Register
DDRSDRC_WPMR
30
22
14
—
Read-write
See
6
Table 22-9
29
21
13
—
5
28
20
12
—
4
WPKEY
WPKEY
WPKEY
27
19
11
—
3
26
18
10
—
2
AT91SAM9G45
25
17
—
9
1
WPEN
24
16
8
0
275