AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 994

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 41-11. Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address
6438F–ATARM–21-Jun-10
Address of
Source Layer
Note:
The DMAC Transfer flow is shown in
18. The DMAC reloads the DMAC_SADDRx register from the initial value. Hardware sets
19. The DMAC fetches the next LLI from memory location pointed to by the current
SADDR
transfer. Only DMAC_CTRLAx register is written out, because only the
DMAC_CTRLAx.BTSIZE and DMAC_CTRLAx.DONE fields have been updated by
hardware within the DMAC. The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate
buffer completion Therefore, software can poll the LLI.DMAC_CTRLAx.DONE field of
the DMAC_CTRLAx register in the LLi to ascertain when a buffer transfer has
completed.
the buffer complete interrupt. The DMAC samples the row number as shown in
41-2 on page
Hardware sets the transfer complete interrupt and disables the channel. You can either
respond to the Buffer Complete or Chained buffer Transfer Complete interrupts, or poll
for the Channel Enable (DMAC_CHSR.ENABLE) bit until it is cleared by hardware, to
detect when the transfer is complete. If the DMAC is not in Row 1 as shown in
2 on page
DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx,
DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. Note that the
DMAC_SADDRx is not re-programmed as the reloaded value is used for the next
DMAC buffer transfer. If the next buffer is the last buffer of the DMAC transfer then the
DMAC_CTRLBx and DMAC_DSCRx registers just fetched from the LLI should match
Row 1 of
ure 41-11 on page
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit
is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was
cleared at the start of the transfer.
Source Buffers
Table 41-2 on page
982, the following step is performed.
982. If the DMAC is in Row 1, then the DMAC transfer has completed.
994.
982. The DMAC transfer might look like that shown in
Figure 41-12 on page
DADDR(N)
DADDR(0)
DADDR(2)
DADDR(1)
Buffer1
Destination Buffers
Buffer0
Buffer2
BufferN
Destination Layer
995.
Address of
AT91SAM9G45
Table 41-
Table
Fig-
994