AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1182

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 46-36. SSC Timings with 3.3V Peripheral Supply (Continued)
Notes:
Table 46-37. SSC Timings with 1.8V Peripheral Supply
Notes:
1182
Symbol
SSC
SSC
SSC
Symbol
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
11
12
13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
(1)
(1)
1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
AT91SAM9G45
(Receive Start Selection), two Periods of the MCK must be added to timings.
RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabilization.
46-18
(Receive Start Selection), two Periods of the MCK must be added to timings.
RK) edge and the signal change. The Max access time is the time between the TK edge and the signal stabilization.
46-18
Parameter
TK edge to TF/TD (TK output, TF output)
TK edge to TF/TD (TK input, TF output)
TF setup time before TK edge (TK output)
TF hold time after TK edge (TK output)
TK edge to TF/TD (TK output, TF input)
TF setup time before TK edge (TK input)
TF hold time after TK edge (TK input)
TK edge to TF/TD (TK input, TF input)
RF/RD setup time before RK edge (RK input)
RF/RD hold time after RK edge (RK input)
RK edge to RF (RK input)
RF/RD setup time before RK edge (RK output)
RF/RD hold time after RK edge (RK output)
RK edge to RF (RK output)
Parameter
RF/RD setup time before RK edge (RK output)
RF/RD hold time after RK edge (RK output)
RK edge to RF (RK output)
illustrates Min and Max accesses for SSC0. The same applies to SSC1, SSC4, and SSC7, SSC10 and SSC13.
illustrates Min and Max accesses for SSC0. The same applies to SSC1, SSC4, and SSC7, SSC10 and SSC13.
Transmitter
Receiver
Cond
Cond
-2.8 (+2*t
5.0 (+3*t
18.4 - t
18.6 - t
14.2 - t
t
t
t
CPMCK
CPMCK
CPMCK
t
t
4.8
5.4
CPMCK
CPMCK
Min
0
Min
0
0
0.6
2.4
CPMCK
CPMCK
(2)
(2)
(2)
CPMCK
CPMCK
CPMCK
(2)
(2)
- 5.1
- 5.1
- 3.9
)
)
(1)(2)
(1)(2)
18.3 (+3*t
4.2 (+2*t
18.4
21.5
4.2
5.3
5.2
Max
Max
CPMCK
CPMCK
(2)
(2)
(2)
(2)
(2)
)
)
(1)(2)
6438F–ATARM–21-Jun-10
(1)(2)
Units
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Figure
Figure