AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1168

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

46.11 Touch Screen ADC (TSADC)
Table 46-21. Channel Conversion Time and ADC Clock
Note:
Table 46-22. External Voltage Reference Input
Table 46-23. Analog Inputs
Table 46-24. Transfer Characteristics
1168
Parameter
ADC Clock Frequency
Startup Time
Track and Hold Acquisition Time (TTH)
Conversion Time (TCT)
Throughput Rate
Parameter
ADVREF Input Voltage Range
ADVREF Average Current
Current Consumption on VDDANA
Parameter
Input Voltage Range
Input Leakage Current
Input Capacitance
Input Impedance
Parameter
Resolution
Integral Non-linearity
Differential Non-linearity
Offset Error
Gain Error
1. The Track and Hold Acquisition Time is given by:
AT91SAM9G45
The ADC internal clock is divided by 2 in order to generate a clock with a duty cycle of 75%. So the maximum conversion
time is give by:
The full speed is obtained for an input source impedance of < 50 Ohms maximum, or TTH = 500 ns.
In order to make the TSADC work properly, the SHTIM field in TSADCC Mode Register is to be calculated according to this
Track and Hold Acquisition Time, also called Sampled and Hold Time.
TTH (ns)
TCT μs
=
=
500
---------- - MHz
Fclk
23
+
0.12
Z
Conditions
Conditions
10-bit resolution mode
Return from Idle Mode
ADC Clock = 13.2 MHz
ADC Clock = 13.2 MHz
ADC Clock = 13.2 MHz
IN
(1)
(1)
(1)
Min
2.4
Min
0
Min
-0.9
-1.5
Min
0.5
Typ
Typ
50
7
Typ
Typ
0.5
10
VDDANA
ADVREF
6438F–ATARM–21-Jun-10
Max
600
300
Max
Max
13.2
1.75
10
Max
+0.9
440
±10
1
40
±2
±2
Ohms
Units
Units
Units
kSPS
Units
MHz
LSB
LSB
LSB
μA
μA
μA
pF
mV
μs
μs
μs
V
V
bit