AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 906

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

39.5.1
Register Name:
Access Type:
Reset Value:
• HSYNC_POL: Horizontal Synchronization Polarity
0: HSYNC active high.
1: HSYNC active low.
• VSYNC_POL: Vertical Synchronization Polarity
0: VSYNC active high.
1: VSYNC active low.
• PIXCLK_POL: Pixel Clock Polarity
0: Data is sampled on rising edge of pixel clock.
1: Data is sampled on falling edge of pixel clock.
• EMB_SYNC: Embedded Synchronization
0: Synchronization by HSYNC, VSYNC.
1: Synchronization by embedded synchronization sequence SAV/EAV.
• CRC_SYNC: Embedded Synchronization Correction
0: No CRC correction is performed on embedded synchronization.
1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in
the status register.
• FRATE: Frame Rate [0..7]
0: All the frames are captured, else one frame every FRATE+1 is captured.
• DISCR: Disable Codec Request
0 = Codec datapath DMA interface requires a request to restart.
1 = Codec datapath DMA automatically restarts.
6438F–ATARM–21-Jun-10
CRC_SYNC
31
23
15
–
7
ISI Configuration 1 Register
EMB_SYNC
30
22
14
6
ISI_CFG1
Read-write
0x00000000
THMASK
29
21
13
5
–
PIXCLK_POL
FULL
28
20
12
4
SFD
SLD
VSYNC_POL
DISCR
27
19
11
3
HSYNC_POL
26
18
10
2
AT91SAM9G45
FRATE
25
17
9
1
–
24
16
8
0
–
906