AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 158

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.1.4
Table 20-1.
20.1.5
20.1.6
158
Name
DDR_D0 - DDR_D15
DDR_A0 - DDR_A13
DDR_DQM0 - DDR_DQM1
DDR_DQS0 - DDR_DQS1
DDR_VREF
DDR_CS
DDR_CLK - DDR_CLK#
DDR_CKE
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA0 - DDR_BA1
AT91SAM9G45
I/O Lines Description
Product Dependencies
Implementation Example
DDR2 I/O Lines Description
The pins used for interfacing the DDR2 memory are not multiplexed with the PIO lines.
The following hardware configuration is given for illustration only. The user should refer to the
memory manufacturer web site to check current device availability.
Function
Data Mask
Data Strobe
Reference Voltage for DDR2 operations, typically 0.9V
Chip Select
DDR2 Differential Clock
Clock enable
Row signal
Column signal
Write enable
Bank Select
Data Bus
Address Bus
DDR2/LPDDR Controller
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
I/O
6438F–ATARM–21-Jun-10
Active Level
High
Low
Low
Low
Low