AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1048

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

42.7.11
Register Name:
Addresses:
Access Type:
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
1048
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
31
23
15
7
256, 512, or 1024). The resulting period formula will be:
256, 512, or 1024). The resulting period formula will be:
------------------------------ -
----------------------------------------- -
---------------------------------------- -
--------------------------------------------------- -
X CPRD
CRPD
2 X CPRD
2 CPRD
AT91SAM9G45
PWM Channel Period Register
MCK
MCK
MCK
MCK
DIVA
DIVA
30
22
14
PWM_CPRD[0..3]
0xFFFB8208 [0], 0xFFFB8228 [1], 0xFFFB8248 [2], 0xFFFB8268 [3]
6
Read/Write
or
--------------------------------------------- -
CRPD
or
--------------------------------------------------- -
2
MCK
CPRD
DIVAB
29
21
13
MCK
5
DIVB
28
20
12
4
CPRD
CPRD
CPRD
CPRD
27
19
11
3
26
18
10
2
25
17
9
1
6438F–ATARM–21-Jun-10
24
16
8
0