AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 973

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41. DMA Controller (DMAC)
41.1
41.2
6438F–ATARM–21-Jun-10
Description
Embedded Characteristics
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses. One channel is
required for each source/destination pair. In the most basic configuration, the DMAC has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also
known as a dual-access transfer.
The DMAC is programmed via the APB interface.
The DMA controller can handle the transfer between peripherals and memory and so receives
the triggers from the peripherals below. The hardware interface numbers are also given below in
Table 41-1
Table 41-1.
Instance Name
MCI0
SPI0
SPI0
SPI1
SPI1
SSC0
SSC0
SSC1
SSC1
AC97C
AC97C
MCI1
• Two Masters
• Embeds 8 channels
• 64 bytes/FIFO for Channel Buffering
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• memory to memory transfer
• Peripheral to memory
• Memory to peripheral
• Acting as two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
DMA Channel Definition
T/R
TX/RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX/RX
DMA Channel HW
interface Number
0
1
2
3
4
5
6
7
8
9
10
13
AT91SAM9G45
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