AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 306

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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AT91SAM9G45
Note:
• If a new value for CSS field corresponds to PLLA Clock,
• If a new value for CSS field corresponds to Main Clock or Slow Clock,
The MDIV field is used to control the Master Clock divider. It is possible to choose between
different values (0, 1, 2, 3). The Master Clock output is Master/Processor Clock Prescaler
output divided by 1, 2, 4 or 3, depending on the value programmed in MDIV.
The PLLADIV2 field is used to control the PLLA Clock divider. It is possible to choose
between different values (0, 1). The PMC PLLA Clock input is divided by 1 or 2, depending
on the value programmed in PLLADIV2.
By default, MDIV and PLLLADIV2 are set to 0, which indicates that Processor Clock is equal
to the Master Clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to
be set in the PMC_SR register. This can be done either by polling the status register or by
waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been
enabled in the PMC_IER register.
The PMC_MCKR register must not be programmed in a single write operation. The preferred
programming sequence for the PMC_MCKR register is as follows:
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY
bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet.
The user must wait for MCKRDY bit to be set again before using the Master and Processor
Clocks.
Code Example:
The Master Clock is main clock divided by 16.
The Processor Clock is the Master Clock.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in
CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again,
LOCK goes high and MCKRDY is set.
While PLLA is unlocked, the Master Clock selection is automatically changed to Main Clock. For
further information, see
Section
25.10.2.
“Clock Switching Waveforms” on page
6438F–ATARM–21-Jun-10
309.