AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 837

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

837
AT91SAM9G45
The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention
of the CPU. This means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit) is
done by hardware.
A transfer descriptor can be used. Instead of programming the register directly, a descriptor
s h o u l d b e p r o g r a m m e d a n d t h e a d d r e s s o f t h i s d e s c r i p t o r i s t h e n g i v e n t o
UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field (Load Next Descrip-
tor Now) in UDPHS_DMACONTROLx register.
The structure that defines this transfer descriptor must be aligned.
Each buffer to be transferred must be described by a DMA Transfer descriptor (see
DMA Channel Transfer Descriptor” on page
cuting transfer of the buffer, the UDPHS may fetch a new transfer descriptor from the memory
address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the
transfer status is updated in the UDPHS_DMASTATUSx register.
To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be
stopped. To do so, INTDIS_DMA and TX_BK_RDY may be set in the UDPHS_EPTCTLENBx
register. It is also possible for the application to wait for the completion of all transfers. In this
case the LDNXT_DSC field in the last transfer descriptor UDPHS_DMACONTROLx register
must be set to 0 and CHANN_ENB set to 1.
Then the application can chain a new transfer descriptor.
The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is trig-
gered. This can be used to stop DMA transfers in case of errors.
The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the
UDPHS_DMACONTROLx register).
– Size of buffer to send: size of the buffer to be sent to the host.
– END_B_EN: The endpoint can validate the packet (according to the values
– END_BUFFIT: generate an interrupt when the BUFF_COUNT in
– CHANN_ENB: Run and stop at end of buffer
programmed in the AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.)
(See
with
UDPHS_DMASTATUSx reaches 0.
DMA)
“UDPHS Endpoint Control Register” on page 876
887). Transfer descriptors are chained. Before exe-
and
Figure 38-12. Autovalid
6438F–ATARM–21-Jun-10
“UDPHS