AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 299

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.8
6438F–ATARM–21-Jun-10
UTMI Bias and Phase Lock Loop Programming
Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt
to the processor. The user has to load the number of Slow Clock cycles required to cover the
PLLA transient time into the PLLACOUNT field.
The PLLA clock can be divided by 2 by writing the PLLADIV2 bit in PMC_MCKR register.
The multiplier is built-in to 40 to obtain the USB High Speed 480 MHz.
Whenever the UPLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR
is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded
in the UPLL counter. The UPLL counter then decrements at the speed of the Slow Clock divided
by 8 until it reaches 0. At this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt
to the processor. The user has to load the number of Slow Clock cycles required to cover the
UPLL transient time into the PLLCOUNT field. The BIAS, needed for High Speed operations, is
enabled by writing BIASEN in CKGR_UCKR once the PLL locked.
MAINCK
SLCK
PLLCOUNT
UPLLEN
Counter
UPLL
UPLL
LOCKU
UPLLCK
AT91SAM9G45
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