AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1204

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1204
Doc. Rev
6438D
Doc. Rev
6438C
Doc. Rev
6438B
AT91SAM9G45
Comments
LCD Controller (LCDC):
Section 45.12.12 “LCD Timing Configuration Register
written to 1’ added to VHDLY definition.
Parallel Input/Output Controller (PIO):
- DELAY Registers were addded in a
description added in a
-
Register”and
In
Clear Output Data”
All ‘slewrate’ changed into ‘drive’.
All ‘IO’ changed into ‘I/O’.
All
Any extra ‘Controller’ or ‘Controller PIO’ removed.
Static Memory Controller (SMC):
Table 21-5 removed from
21-8
USB Host Port:
Section 37. “USB High Speed Host Port (UHPHS)”
Comments
Introduction:
Section 3. “Signal Description”
concerning NRST configuration.
Section 4. “Package and
Boot Program:
Section 11.5.2.1 “Supported External Crystal/External
RSTC:
Section 12.5 “Reset Controller (RSTC) User Interface” Table 12-1
0x0000 0001.
Comments
DDRSDRC:
Section 22.7.3 “DDRSDRC Configuration
Section 22.7.9 “DDRSDRC DLL Register”
removed from register.
“Write Protected Registers”
Section 30.6.11 “PIO Clear Output Data
Section 30.6 “Parallel Input/Output Controller (PIO) User Interface”
instead.
Section 30.6.32 “PIO Write Protect Status
Section 30.6.30 “PIO I/O Delay
Pinout”,
Section 21.8.6 “Reset Values of Timing
description added, together with
,
Table
Table 4-1
Section 30.4.12 “Programmable I/O Delays”
3-1, in
Register”, bit named ENRDM removed from register.
bits named, SDCOVF, SDCUDF, SDERF, SDVAL, SDCVAL
Register”, “P0-P31: Set Output Data” changed into “P0-P31:
updated.
“Reset/Test”
, HS (High Speed) was added to the title.
1”, ‘-’ replaced by ‘1’ for bit 31, and ‘Bit 31 must be
Clocks”, ...”supports 12 MHz”...
Register”.
Register”.
description, NRST pin updated with note
Section 30.6.31 “PIO Write Protect Mode
Parameters”. Cross-referenced
Mode register backup reset value is
headers now start with ‘PIO’ only.
and associated register
Table
6438F–ATARM–21-Jun-10
Change
Request
Ref.
6685
6715
6742
6644
Change
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6600
6639
6598
6639
Change
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6606