AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1202

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1202
Doc. Rev
6438F
Doc. Rev
6438E
AT91SAM9G45
Comments
USART
- LIN Mode condition now shown in
Transmitter
Comments
Introduction:
“Two Three-channel 32-bit Timer/Counters” peripheral feature changed into
16-bit Timer/Counters”
ECC row added to
Typos corrected in
RNG --> TRNG (also in
Bus Matrix (MATRIX):
Figure 19-1 “DDR
1 row and 1 column added to
DDR/SDR SDRAM Controller (DDRSDRC):
“NO_OPTI” bit removed.
“DIS_ANTICIP_READ”
Electrical Characteristics:
Section 46.14 “DDRSDRC
Section 46.11 “Touch Screen ADC
Last sentence in the Note added.
SPI Master Mode figure titles reversed between
SPI Master and Slave Mode figure titles edited again, from
Figure 46-8 “SPI Slave Mode 1 and 2”
Table 46-2
Ethernet MAC 10/100 (EMAC):
Wake-on-LAN feature activated, including
“Wake-on-LAN
EMAC interrupt on Wake-on-LAN Event activated.
Peripheral DMA Controller (PDC):
Typos corrected in
Power Management Controller (PMC):
Section 25.11.13 “PMC Programmable Clock
Universal Synchronous Asynchronous Receiver Transmitter (USART):
Section 33. “Universal Synchronous Asynchronous Receiver Transmitter
‘DC Characteristics’, I
(USART)”.
Register”.
Table
Table
Figure 6-1 “AT91SAM9G45 Memory Mapping”
Multi-port”, and text above and below added.
.
description edited.
Figure 2-1
8-1: AC97 --> AC97C (also in
23-1: AC97 --> AC97C and TSDAC --> TSADCC
Timings”, list of
Table 19-3
SC
and
(TSADC)”, TTH (ns) formula edited.
Section 33. “Universal Synchronous Asynchronous Receiver
values changed.
Table
and
Section 35.4.12 “Wake-on-LAN Support”
Supported speed grade limitations updated.
Table
46-4)
Register”, CSS and SLCMCK fields edited.
Figure 46-5
19-4.
Table 23-1
Figure 46-5 “SPI Master Mode 1 and 2”
and
Figure
and
Table
46-6.
(USART)”, SPI feature added.
41-1), PWMC --> PWM,
“Two Three-channel
and
Section 35.6.26
to
6438F–ATARM–21-Jun-10
Change
Request
Ref.
6944
Change
Request
Ref.
6828
6842
RFO
6797
6871
6776
6800
RFO
6847
6872
6903
6836
6838
RFO
6844
6837