AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 258

MCU ARM9 324-TFBGA

AT91SAM9G45-CU

Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM9G45-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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22.6
Figure 22-26. Programmable IO Delays
22.7
The User Interface is connected to the APB bus.
258
Programmable IO Delays
DDR-SDRAM Controller (DDRSDRC) User Interface
AT91SAM9G45
SMC
The external bus interface consists of a data bus, an address bus and control signals. The simul-
taneous switching outputs on these busses may lead to a peak of current in the internal and
external power supply lines.
In order to reduce the peak of current in such cases, additional propagation delays can be
a d j u s t e d i n d e p e n d e n t l y f o r p a d b u f f e r s b y m e a n s o f c o n f i g u r a t i o n r e g i s t e r s ,
DDRSDRC_DELAY1-8.
The additional programmable delays for each IO range from 0 to
delay can differ between IOs supporting this feature. Delay can be modified per programming for
each IO. The minimal additional delay that can be programmed on a PAD supporting this feature
is 1/16 of the maximum programmable delay.
When programming 0x0 in fields “Delay1 to Delay8”, no delay is added (reset value) and the
propagation delay of the pad buffers is the inherent delay of the pad buffer. When programming
0xF in field “Delay1” the propagation delay of the corresponding pad is maximal.
D D R S D R C _ D E L A Y 1 , D D R S D R C _ D E L A Y 2 a l l o w t o c o n f i g u r e d e l a y o n D [ 1 5 : 0 ] ,
DDRSDRC_DELAY1[3:0] corresponds to D[0] and DDRSDRC_DELAY2[3:0] corresponds to
D[8].
D D R S D R C _ D E L A Y 3 , D D R S D R C _ D E L A Y 4 a l l o w t o c o n f i g u r e d e l a y o n A 1 3 : 0 ] ,
DDRSDRC_DELAY3[3:0] corresponds to A[0] and DDRSDRC_DELAY4[3:0] corresponds to
A[8].
DELAY1
DELAYx
DELAYy
DELAY2
D_out[0]
D_out[1]
D_out[n]
D_in[0]
D_in[1]
D_in[n]
A[m]
Programmable Delay Line
Programmable Delay Line
Programmable Delay Line
Programmable Delay Line
4
ns (Worst Case PVT). The
D[0]
D[1]
D[n]
A[m]
6438F–ATARM–21-Jun-10

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