AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 963

MCU ARM9 324-TFBGA

AT91SAM9G45-CU

Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM9G45-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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40.11.8
Register Name:
Address:
Access Type:
• EOCx: End of Conversion x
0 = Corresponding analog channel is disabled, or the conversion is not finished.
1 = Corresponding analog channel is enabled and conversion is complete.
• OVREx: Overrun Error x
0 = No overrun error on the corresponding channel since the last read of TSADCC_SR.
1 = There has been an overrun error on the corresponding channel since the last read of TSADCC_SR.
• DRDY: Data Ready
0 = No data has been converted since the last read of TSADCC_LCDR.
1 = At least one data has been converted and is available in TSADCC_LCDR.
• GOVRE: General Overrun Error
0 = No General Overrun Error occurred since the last read of TSADCC_SR.
1 = At least one General Overrun Error has occurred since the last read of TSADCC_SR.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in TSADCC_RCR or TSADCC_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TSADCC_RCR or TSADCC_RNCR.
• RXBUFF: RX Buffer Full
0 = TSADCC_RCR or TSADCC_RNCR have a value other than 0.
1 = Both TSADCC_RCR and TSADCC_RNCR have a value of 0.
• PENCNT: Pen Contact
0 = No contact has been detected since the last read of TSADCC_SR or PENDET is at 0.
1 = At least one contact has been detected since the last read of TSADCC_SR.
• NOCNT: No Contact
0 = No contact loss has been detected since the last read of TSADCC_SR or PENDET is at 0.
1 = At least one contact loss has been detected since the last read of TSADCC_SR.
6438F–ATARM–21-Jun-10
OVRE7
EOC7
31
23
15
7
TSADCC Status Register
OVREZ2
OVRE6
EOC6
30
22
14
TSADCC_SR
0xFFFB001C
Read-only
6
OVREZ1
NOCNT
OVRE5
EOC5
29
21
13
5
OVREXP
PENCNT
OVRE4
EOC4
28
20
12
4
RXBUFF
OVRE3
EOC3
27
19
11
3
ENDRX
EOCZ2
OVRE2
EOC2
26
18
10
2
AT91SAM9G45
GOVRE
EOCZ1
OVRE1
EOC1
25
17
9
1
EOCXP
OVRE0
DRDY
EOC0
24
16
8
0
963

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