AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 242

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

To comply with SDRAM timing parameters, additional clock cycles are inserted between pre-
charge/active (Trp) commands and active/read (Trcd) commands. The DDRSDRC supports a
cas latency of two, two and half, and three (2 or 3 clocks delay). During this delay, the controller
uses internal signals to anticipate the next access and improve the performance of the control-
ler. Depending on the latency(2/3), the DDRSDRC anticipates 2 or 3 read accesses. In the case
of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy
mode, etc.), the next access is treated as an incrementing burst of unspecified length, and in
function of the latency(2/3), the DDRSDRC anticipates 2 or 3 read accesses.
For a definition of timing parameters, refer to
Section 22.7.3 “DDRSDRC Configuration Register”
on page
262.
Read accesses to the SDRAM are burst oriented and the burst length is programmed to 8. It
determines the maximum number of column locations that can be accessed for a given read
command. When the read command is issued, 8 columns are selected. All accesses for that
burst take place within these eight columns, meaning that the burst wraps within these 8 col-
umns if the boundary is reached. These 8 columns are selected by addr[13:3]; addr[2:0] is used
to select the starting location within the block.
In the case of incrementing burst (INCR/INCR4/INCR8/INCR16), the addresses can cross the
16-byte boundary of the SDRAM device. For example, when a transfer (INCR4) starts at
address 0x0C, the next access is 0x10, but since the burst length is programmed to 8, the next
access is 0x00. Since the boundary is reached, the burst wraps. The DDRSDRC takes into
account this feature of the SDRAM device. In the case of DDR-SDRAM devices, transfers start
at address 0x04/0x08/0x0C. In the case of SDR-SDRAM devices, transfers start at address
0x14/0x18/0x1C. Two read commands are issued to avoid wrapping when the boundary is
reached. The last read command may generate additional reading (1 read cmd = 4 DDR words
or 1 read cmd = 8 SDR words).
To avoid additional reading, it is possible to use the burst stop command to truncate the read
burst and to decrease power consumption.
AT91SAM9G45
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6438F–ATARM–21-Jun-10