AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 797

MCU ARM9 324-TFBGA

AT91SAM9G45-CU

Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM9G45-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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36.13.6
Name:
Addresses:
Access:
This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only
writeable by an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted
or modified.
• CMDNB: Command Number
• RSPTYP: Response Type
• SPCMD: Special Command
6438F–ATARM–21-Jun-10
31
23
15
7
0
0
1
1
0
0
0
0
1
HSMCI Command Register
RSPTYP
RSP
30
22
14
HSMCI_CMDR
0xFFF80014 (0), 0xFFFD0014 (1)
Write-only
6
SPCMD
0
0
1
1
0
0
1
0
1
29
21
13
Response Type
No response.
48-bit response.
136-bit response.
R1b response type
5
0
1
0
1
0
MAXLAT
TRTYP
28
20
12
4
Command
Not a special CMD.
Initialization CMD:
74 clock cycles for initialization sequence.
Synchronized CMD:
Wait for the end of the current data block transfer before sending the
pending command.
CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command
completion signal on the command line.
Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
BOOT_ACK
OPDCMD
27
19
11
3
CMDNB
ATACS
TRDIR
26
18
10
2
AT91SAM9G45
SPCMD
25
17
9
1
IOSPCMD
TRCMD
24
16
8
0
797

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