AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1059

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 43-5. Audio Transfer (PCM L Front, PCM R Front) on Channel x
43.7.3.3
43.7.3.4
1059
(Controller Output)
Write access to
AC97C_THRx
(AC97C_SR)
(AC97C_SR)
TXEMPTY
TXRDYCx
AT91SAM9G45
AC97FS
AC97TX
Slot #
AC97 Output Frame
Receive Operation
TAG
0
transfered to the shift register
The TXEMPTY flag in the AC97 Controller Channel x Status Register (AC97C_CxSR) is set
when all requested transmissions for a channel have been shifted on the AC-link. The applica-
tion can either poll TXEMPTY flag in AC97C_CxSR or wait for an interrupt notice associated
with the same flag.
In most cases, the AC97 Controller is embedded in chips that target audio player devices. In
such cases, the AC97 Controller is exposed to heavy audio transfers. Using the polling tech-
nique increases processor overhead and may fail to keep the required pace under an operating
system. In order to avoid these polling drawbacks, the application can perform audio streams by
using PDC connected to channel A, which reduces processor overhead and increases perfor-
mance especially under an operating system.
The PDC transmit counter values must be equal to the number of PCM samples to be transmit-
ted, each sample goes in one slot.
The AC97 Controller outputs a thirteen-slot frame on the AC-Link. The first slot (tag slot or slot 0)
flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data
or not. Slots 1 and 2 are used if the application performs control and status monitoring actions
on AC97 Codec control/status registers. Slots [3:12] are used according to the content of the
AC97 Controller Output Channel Assignment Register (AC97C_OCA). If the application per-
forms many transmit requests on a channel, some of the slots associated to this channel or all of
them will carry valid data.
The AC97 Controller can also receive data from AC97 Codec. Data is received in the channel’s
shift register and then transferred to the AC97 Controller Channel x Read Holding Register. To
read the newly received data, the application must perform the following steps:
• Poll RXRDY flag in AC97 Controller Channel x Status Register (AC97C_CxSR). x being one
• Read data from AC97 Controller Channel x Read Holding Register.
ADDR
of the 2 channels.
CMD
1
transfered to the shift register
PCM L Front
DATA
CMD
2
PCM R Front
L Front
3
PCM
R Front
4
PCM
LINE 1
DAC
5
Center
6
PCM
L SURR
PCM
7
R SURR
PCM
8
PCM
LFE
9
LINE 2
DAC
10
6438F–ATARM–21-Jun-10
11
HSET
DAC
CTRL
12
IO