AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 241

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 22-10. SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device
22.4.2
6438F–ATARM–21-Jun-10
COMMAND
DQS[1:0]
DM[1:0]
SDCLK
BA[1:0]
D[15:0]
A[12:0]
SDRAM Controller Read Cycle
NOP PRCHG NOP
0
3
The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever
access type, the DDRSDRC keeps track of the active row in each bank, thus maximizing perfor-
mance of the DDRSDRC.
The SDRAM devices are programmed with a burst length equal to 8 which determines the length
of a sequential data output by the read command that is set to 8. The latency from read com-
mand to data output is equal to 2 or 3. This value is programmed during the initialization phase
(see
To initiate a single access, the DDRSDRC checks if the page access is already open. If
row/bank addresses match with the previous row/bank addresses, the controller generates a
read command. If the bank addresses are not identical or if bank addresses are identical but the
row addresses are not identical, the controller generates a precharge command, activates the
new row and initiates a read command. To comply with SDRAM timing parameters, additional
clock cycles are inserted between precharge/active (Trp) commands and active/read (Trcd)
command. After a read command, additional wait states are generated to comply with cas
latency. The DDRSDRC supports a cas latency of two, two and half, and three (2 or 3 clocks
delay). As the burst length is fixed to 8, in the case of single access or burst access inferior to 8
data requests, it has to stop the burst otherwise seven or X values could be read. Burst Stop
Command (BST) is used to stop output during a burst read.
To initiate a burst access, the DDRSDRC checks the transfer type signal. If the next accesses
are sequential read accesses, reading to the SDRAM device is carried out. If the next access is
a read non-sequential access, then an automatic page break can be inserted. If the bank
addresses are not identical or if bank addresses are identical but the row addresses are not
identical, the controller generates a precharge command, activates the new row and initiates a
read command. In the case where the page access is already open, a read command is
generated.
Row a
Section 22.3.1 “SDR-SDRAM Initialization” on page
ACT
NOP WRITE
col a
NOP
Da
0
Db
3
Data masked
twtr
231).
READ
AT91SAM9G45
NOP
Da Db
241