AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 948

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6438F–ATARM–21-Jun-10
The vertical position can be easily calculated by dividing the data at offset 0 (X
at offset 1 (Y
The horizontal position can be easily calculated by dividing the data at offset 2 (Y
data at offset 3 (X
if the bit PRES in
measure both position and pressure.
The resulting buffer is 16 bits wide and its structure stored in memory is:
1. X
2. Y
3. Y
4. X
5. AD4 to AD7 if enabled.
1. If SLEEP is set, wake up the ADC cell and wait for the Startup Time.
2. Close the switches on the inputs X
3. Convert Channel X
4. Close the switches on the inputs X
5. Convert Channel Y
6. Close the switches on the inputs X
7. Convert Channel X
8. Close the switches on the inputs X
9. Convert Channel X
10. Close the switches on the inputs X
11. Convert Channel Y
12. Close the switches on the inputs Y
13. Convert Channel Y
14. Close the switches on the inputs Y
15. Convert Channel Y
16. Close the switches on the inputs Y
17. Convert Channel X
18. if Channel 4 to channel 7are enabled, convert the channels and store result in the cor-
19. If SLEEP is set, sleep down the ADC cell.
1. Z1
2. Z2
3. X
4. Y
5. Xpos
6. Y
result in both TSADCC_CDR0 and TSADCC_LCDR.
from the result and store the subtraction result in both TSADCC_CDR1 and
TSADCC_LCDR.
TSADCC_XPDR in TSADCC_LCDR.
result in both TSADCC_CDR2 and TSADCC_LCDR.
result in both TSADCC_CDR3 and TSADCC_LCDR.
responding TSADCC_CDRx and TSADCC_LCDR
P
P
P
P
P
P
P
- X
- X
- Y
- Y
- X
- X
- Y
M
M
M
M
M
M
M
P
- X
M
P
“TSADCC Mode Register”
).
- Y
M
).
p
M
p,
P
p
p
M
M
subtract TSADCC_CDR3 from the result and store the subtraction
subtract TSADCC_CDR3 from the result and store the subtraction
and store the result in both TSADCC_Z1DR and TSADCC_LCDR.
subtract TSADCC_CDR1 from the result and store the subtraction
and store the result in TSADCC_XPDR, subtract TSADCC_CDR1
and store the result in both TSADCC_Z2DR and TSADCC_LCDR.
and store the result in TSADCC_CDR1.
and store the result in TSADCC_CDR3 while storing content of
M
M
P
P
P
P
P
P
and X
and X
and X
and Y
and Y
and Y
and Y
and Y
is enabled, the following sequence is performed to
M
M
M
M
M
M
p
P
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
AT91SAM9G45
P
- X
M
P
) by the data
- Y
M
) by the
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