AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 613

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

33.7.8.23
Figure 33-52. Master Node with PDC (PDCM=1)
6438F–ATARM–21-Jun-10
WRITE BUFFER
IDENTIFIER
CHKTYP
CHKDIS
PARDIS
DATA N
DATA 0
FSDIS
NACT
DLM
DLC
|
|
|
|
Master Node Configuration
(DMA)
PDC
The PDC uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The PDC
always writes in the Transmit Holding register (US_THR) and it always reads in the Receive
Holding register (US_RHR). The size of the data written or read by the PDC in the USART is
always a byte.
The user can choose between two PDC modes by the PDCM bit in the LIN Mode register
(US_LINMR):
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response
(NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT =
SUBSCRIBE).
• PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDC in
• PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by
the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR).
Because the PDC transfer size is limited to a byte, the transfer is split into two accesses.
During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FDIS are
written. During the second access the 8-bit DLC field is written.
the user in the LIN Mode register (US_LINMR).
APB bus
RXRDY
NODE ACTION = PUBLISH
LIN CONTROLLER
USART3
WRITE BUFFER
READ BUFFER
IDENTIFIER
CHKTYP
PARDIS
CHKDIS
DATA N
DATA 0
FSDIS
NACT
DLM
DLC
|
|
|
|
(DMA)
PDC
AT91SAM9G45
APB bus
RXRDY
TXRDY
NODE ACTION = SUBSCRIBE
LIN CONTROLLER
USART3
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