AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 133

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 19-3.
6438F–ATARM–21-Jun-10
1
2
3
4
5
6
7
0
Internal SRAM 0
Internal Periph.
Master
Internal ROM
LCD User Int.
UDPHS RAM
Slave
DDR Port 0
DDR Port 1
DDR Port 2
DDR Port 3
UHP OHCI
UHP EHCI
Reserved
EBI
AT91SAM9G45 Masters to Slaves Access DDRMP_DIS = 0
926 Instr.
ARM
X
X
X
X
X
X
X
X
X
X
0
-
-
-
Figure 19-1. DDR Multi-port
• When the DDR multi-port is enabled (DDRMP_DIS=0), the ARM instruction and data are
• When the DDR multi-port is disabled (DDRMP_DIS=1), DDR Port 1 is dedicated to the LCD
respectively connected to DDR Port 0 and DDR Port 1. The other masters share DDR Port 2
and DDR Port 3.
controller. The remaining masters share DDR Port 2 and DDR Port 3.
926 Data
ARM
1
X
X
X
X
X
X
X
X
X
X
-
-
-
PDC
X
2
X
X
X
X
X
-
-
-
-
-
-
-
USB Host
OHCI
DMA
LCD
3
X
X
X
X
-
-
-
-
-
-
-
-
-
4 & 5
DMA
X
X
X
X
X
-
-
-
-
-
-
-
-
MATRIX
DMA
ISI
X
X
X
X
6
-
-
-
-
-
-
-
-
-
ARM D
DMA
LCD
X
X
7
-
-
-
-
-
-
-
-
-
-
-
Ethernet
DDRMP_DIS
MAC
8
X
X
X
X
-
-
-
-
-
-
-
-
-
AT91SAM9G45
Device HS
DDR_S2
DDR_S1
DDR_S3
USB
X
X
X
X
X
9
-
-
-
-
-
-
-
-
USB Host
EHCI
10
X
X
X
X
-
-
-
-
-
-
-
-
-
Reserved
11
X
X
-
-
-
-
-
-
-
-
-
-
-
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