AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 1120

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

45.7
45.8
1120
Interrupts
Configuration Sequence
AT91SAM9G45
The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal
LCD Core Clock. The IRQs are:
Each IRQ can be individually enabled, disabled or cleared, in the LCD_IER (Interrupt Enable
Register), LCD_IDR (Interrupt Disable Register) and LCD_ICR (Interrupt Clear Register) regis-
ters. The LCD_IMR register contains the mask value for each IRQ source and the LDC_ISR
contains the status of each IRQ source. A more detailed description of these registers can be
found in
The DMA Controller starts to transfer image data when the LCDC Core is activated (Write to
LCD_PWR field of PWRCON register). Thus, the user should configure the LCDC Core and
configure and enable the DMA Controller prior to activation of the LCD Controller. In addition,
the image data to be shows should be available when the LCDC Core is activated, regardless of
the value programmed in the GUARD_TIME field of the PWRCON register.
To disable the LCD Controller, the user should disable the LCDC Core and then disable the
DMA Controller. The user should not enable LIP again until the LCDC Core is in IDLE state. This
is checked by reading the LCD_BUSY bit in the PWRCON register.
The initialization sequence that the user should follow to make the LCDC work is:
• DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB
• FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when
• FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO
• DMA end of frame IRQ. Generated when the DMA controller updates the Frame Base
• End of Line IRQ. This IRQ is generated when the LINEBLANK period of each line is reached
• End of Last Line IRQ. This IRQ is generated when the LINEBLANK period of the last line of
• Create or copy the first image to show in the display buffer memory.
• If a palletized mode is used, create and store a palette in the internal LCD Palette
•
slave while it is doing a data transfer.
the FIFO is empty.
while the FIFO is full.
Address pointers. This IRQ can be used to implement a double-buffer technique. For more
information, see
and the DMA Controller is in inactive state.
the current frame is reached and the DMA Controller is in inactive state.
memory(See “Palette” on page 1104.
Configure the LCD Controller Core without enabling it:
– LCDCON1 register: Program the CLKVAL and BYPASS fields: these fields control the
pixel clock divisor that is used to generate the pixel clock LCDDOTCK. The value to
program depends on the LCD Core clock and on the type and size of the LCD
Module used. There is a minimum value of the LCDDOTCK clock period that
depends on the LCD Controller Configuration, this minimum value can be found in
Table 45-14 on page
pixel clock divisor can be found at the end of the section
“LCD Controller (LCDC) User Interface” on page
“Double-buffer Technique” on page
1109. The equations that are used to calculate the value of the
1122.
1125.
“Timegen” on page 1108
6438F–ATARM–21-Jun-10