AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 233

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.3.3
6438F–ATARM–21-Jun-10
DDR2-SDRAM Initialization
The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized
by the following sequence:
A minimum pause of 200 μs is provided to precede any signal toggle.
Note:
9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
10. Perform a write access to any low-power DDR1-SDRAM address.
11. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see
12. After initialization, the low-power DDR1-SDRAM device is fully functional.
1. Program the memory device type into the Memory Device Register (see
2. Program the features of DDR2-SDRAM device into the Timing Register (asynchronous
3. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
4. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
5. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
6. An Extended Mode Register set (EMRS2) cycle is issued to chose between commer-
7. An Extended Mode Register set (EMRS3) cycle is issued to set all registers to “0”. The
Section 22.7.1 on page
power DDR1-SDRAM to acknowledge this command.
page
SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz fre-
quency, the refresh timer count register must to be set with (15.625 /100 MHz) = 1562
i.e. 0x061A or (7.81 /100 MHz) = 781 i.e. 0x030d
on page
timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows,
banks, cas latency and output drive strength) (see
22.7.4 on page 265
the Mode Register, the application must set Mode to 1 in the Mode Register (see
tion 22.7.1 on page
acknowledge this command. Now clocks which drive DDR2-SDRAM device are
enabled.
the Mode Register, the application must set Mode to 1 in the Mode Register (see
tion 22.7.1 on page
acknowledge this command. Now CKE is driven high.
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
SDRAM address to acknowledge this command
cial or high temperature operations. The application must set Mode to 5 in the Mode
Register (see
SDRAM to acknowledge this command. The write address must be chosen so that
BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access
should be done at the address 0x20800000.
application must set Mode to 5 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20C00000.
This address is for example purposes only. The real address is dependent on implementation in
the product.
261). (Refresh rate = delay between refresh cycles). The low-power DDR1-
271).
Section 22.7.1 on page
260). Perform a write access to any DDR2-SDRAM address to
260). Perform a write access to any DDR2-SDRAM address to
and
Section 22.7.1 on page
260) and performing a write access at any location in the low-
Section 22.7.5 on page
260) and perform a write access to the DDR2-
260). Perform a write access to any DDR2-
267).
Section 22.7.3 on page
Section 22.7.1 on page
AT91SAM9G45
Section 22.7.8
262,
Section
Sec-
Sec-
260)
233