AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 134
AT91SAM9G45-CU
Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-CU.pdf
(10 pages)
Specifications of AT91SAM9G45-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9G45-CU
Manufacturer:
ATMEL
Quantity:
1 000
Company:
Part Number:
AT91SAM9G45-CU
Manufacturer:
Atmel
Quantity:
31
Part Number:
AT91SAM9G45-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Table 19-4.
19.3
19.4
134
1
2
3
4
5
6
7
0
Internal SRAM 0
Memory Mapping
Special Bus Granting Mechanism
Master
Internal Periph.
Slave
LCD User Int.
UDPHS RAM
Internal ROM
AT91SAM9G45
DDR Port 0
DDR Port 1
DDR Port 2
DDR Port 3
UHP OHCI
UHP EHCI
Reserved
EBI
AT91SAM9G45 Masters to Slaves Access with DDRMP_DIS = 1 (default)
926 Instr.
ARM
.
Table 19-5
the Remap status (RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and
the BMS state at reset.
Table 19-5.
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each
AHB master several memory mappings. In fact, depending on the product, each memory area
may be assigned to several slaves. Booting at the same address while using different AHB
slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that
performs remap action for every master independently.
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
0
X
X
X
X
X
X
X
X
X
X
-
-
-
Base Address
0x0000 0000
926 Data
Slave
ARM
1
X
X
X
X
X
X
X
X
X
X
-
-
-
summarizes the Slave Memory Mapping for each connected Master, depending on
Internal Memory Mapping
PDC
2
X
X
X
X
X
X
-
-
-
-
-
-
-
HOST
Internal ROM
OHCI
USB
BMS = 1
3
X
X
X
X
-
-
-
-
-
-
-
-
-
4 & 5
DMA
X
X
X
X
X
-
-
-
-
-
-
-
-
RCBx = 0
DMA
ISI
6
X
X
X
X
-
-
-
-
-
-
-
-
-
EBI NCS0
BMS
Master
DMA
LCD
7
X
X
-
-
-
-
-
-
-
-
-
-
-
= 0
Ethernet
MAC
8
X
X
X
X
-
-
-
-
-
-
-
-
-
Device HS
Internal SRAM
USB
RCBx = 1
9
X
X
X
X
X
-
-
-
-
-
-
-
-
6438F–ATARM–21-Jun-10
USB Host
EHCI
10
X
X
X
X
-
-
-
-
-
-
-
-
-
Reserved
11
X
X
-
-
-
-
-
-
-
-
-
-
-
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