AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 230

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.2
Figure 22-1.
230
AHB Slave Interface 0
AHB Slave Interface 1
AHB Slave Interface 2
AHB Slave Interface 3
DDRSDRC Module Diagram
AT91SAM9G45
DDRSDRC Module Diagram
APB
DDRSDRC is partitioned in two blocks (see
• An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four
• A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
AHB masters and integrates an arbiter.
Stage
Stage
Stage
Stage
Input
Input
Input
Input
Interconnect Matrix
Interface APB
Output
Arbiter
Stage
SDRAM Signal Management
Asynchronous Timing
Refresh Management
DDR-SDR Controller
Finite State Machine
Power Management
Memory Controller
Figure
22-1):
Addr, DQM
ras,cas,we
cke
clk/nclk
Data
DQS
odt
6438F–ATARM–21-Jun-10
DDR-SDR
Devices