AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 255

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.5
22.5.1
Table 22-1.
Table 22-2.
6438F–ATARM–21-Jun-10
27
27
26
26
Bk[1:0]
Software Interface/SDRAM Organization, Address Mapping
25
25
SDRAM Address Mapping for 16-bit Memory Data Bus Width
Bk[1:0]
Bk[1:0]
24
24
Linear Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
Linear Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
Bk[1:0]
Bk[1:0]
23
23
Bk[1:0]
Bk[1:0]
22
22
Bk[1:0]
The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps
different memory types depending on the values set in the DDRSDRC Configuration Register.
See
trate the relation between CPU addresses and columns, rows and banks addresses for 16-bit
memory data bus widths and 32-bit memory data bus widths.
The DDRSDRC supports address mapping in linear mode .
Linear mode is a method for address mapping where banks alternate at each last SDRAM page
of current bank.
.
The DDRSDRC makes the SDRAM devices access protocol transparent to the user.
to
the device structure. Various configurations are illustrated.
21
21
Table 22-8
Section 22.7.3 “DDRSDRC Configuration Register” on page
20
20
Row[11:0]
19
19
Row[10:0]
Row[11:0]
illustrate the SDRAM device memory mapping seen by the user in correlation with
18
18
Row[10:0]
Row[11:0]
17
17
Row[10:0]
Row[11:0]
16
16
Row[10:0]
15
15
CPU Address Line
CPU Address Line
14
14
13
13
12
12
11
11
(1)
10
10
and Four Banks
9
9
8
8
Column[11:0]
Column[11:0]
7
7
Column[10:0]
Column[10:0]
262. The following figures illus-
Column[9:0]
Column[9:0]
AT91SAM9G45
6
6
Column[8:0]
Column[8:0]
5
5
4
4
3
3
2
2
Table 22-1
1
1
M0
M0
M0
M0
M0
M0
M0
M0
255
0
0