AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 232

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.3.2
232
AT91SAM9G45
Low-power DDR1-SDRAM Initialization
After initialization, the SDR-SDRAM device is fully functional.
The initialization sequence is generated by software. The low-power DDR1-SDRAM devices are
initialized by the following sequence:
A minimum pause of 200 μs will be provided to precede any signal toggle.
Note:
10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see
1. Program the memory device type into the Memory Device Register (see
2. Program the features of the low-power DDR1-SDRAM device into the Configuration
3. Program temperature compensated self refresh (tcr), Partial array self refresh (pasr)
4. An NOP command will be issued to the low-power DDR1-SDRAM. Program NOP com-
5. An all banks precharge command is issued to the low-power DDR1-SDRAM. Program
6. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
7. An Extended Mode Register set (EMRS) cycle is issued to program the low-power
8. A Mode Register set (MRS) cycle is issued to program the parameters of the low-power
page
requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz frequency, the refresh
timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81
/100 MHz) = 781 i.e. 0x030d
on page
Register: asynchronous timing (trc, tras, etc.), number of columns, rows, banks, cas
latency. See
22.7.5 on page
and Drive strength (ds) into the Low-power Register. See
mand into the Mode Register, the application must set Mode to 1 in the Mode Register
(see
address to acknowledge this command. Now clocks which drive DDR1-SDRAM device
are enabled.
all banks precharge command into the Mode Register, the application must set Mode to
2 in the Mode Register (See
any low-power DDR1-SDRAM address to acknowledge this command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see
SDRAM location twice to acknowledge these commands.
DDR1-SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in
the Mode Register (see
SDRAM to acknowledge this command. The write address must be chosen so that
BA[1] is set to 1 BA[0] is set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows,
9 columns, 4 banks) bank address, the low-power DDR1-SDRAM write access should
be done at the address 0x20800000.
DDR1-SDRAM devices, in particular CAS latency, burst length. The application must
set Mode to 3 in the Mode Register (see
write access to the low-power DDR1-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128
MB low-power DDR1-SDRAM (12 rows, 9 columns, 4 banks) bank address, the
SDRAM write access should be done at the address 0x20000000
This address is for example purposes only. The real address is dependent on implementation in
the product.
Section 22.7.1 on page
Section 22.7.1 on page
261). (Refresh rate = delay between refresh cycles). The SDR-SDRAM device
271).
Section 22.7.3 on page
267.
Section 22.7.1 on page
Section 22.7.1 on page
260). Perform a write access to any DDR1-SDRAM
260). Perform a write access to any low-power DDR1-
262,
Section 22.7.1 on page
Section 22.7.4 on page 265
260) and perform a write access to the
260). Perform a write access to
Section 22.7.7 on page
260) and perform a
and
6438F–ATARM–21-Jun-10
Section 22.7.8
Section
269.