AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 944

• Manufacturer Part Number: AT91SAM9G45-CU
• Description: MCU ARM9 324-TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 800 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

40.8
944
Conversion Results
AT91SAM9G45
When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and
stored in the
“TSADCC Last Converted Data
The channel EOC bit and the bit DRDY in the
PDC channel is enabled, DRDY rising triggers a data transfer. In any case, either EOC and
DRDY can trigger an interrupt.
Reading one of the
sponding EOC bit.
Reading
sponding to the last converted channel.
Figure 40-5. EOCx and DRDY Flag Behavior
If the
converted, the corresponding Overrun Error (OVRE) flag is set in the
Register”.
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun
Error) in the
The OVRE and GOVRE flags are automatically cleared when the
read.
“TSADCC Channel Data Register x (x = 0..7)”
(ADC_CHSR)
“TSADCC Last Converted Data Register”
(ADC_SR)
(ADC_SR)
EOCx
DRDY
“TSADCC Status
“TSADCC Channel Data Register x (x = 0..7)”
CHx
Write the ADC_CR
with START = 1
“TSADCC Channel Data Register x (x = 0..7)”
SHTIM
Conversion
Register”.
Time
Register”.
Read the ADC_CDRx
“TSADCC Status Register”
clears the DRDY bit and the EOC bit corre-
is not read before further incoming data is
Write the ADC_CR
with START = 1
of the current channel and in the
SHTIM
“TSADCC Status
Conversion
registers clears the corre-
Time
Read the ADC_LCDR
are both set. If the
6438F–ATARM–21-Jun-10
“TSADCC Status
Register”is