AT91SAM9G45-CU Atmel, AT91SAM9G45-CU Datasheet - Page 604

MCU ARM9 324-TFBGA

AT91SAM9G45-CU

Manufacturer Part Number
AT91SAM9G45-CU
Description
MCU ARM9 324-TFBGA
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM9G45-CU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
800 MHz
Number Of Programmable I/os
160
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
AT91SAM9G45-EKES - KIT EVAL FOR AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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33.7.8.9
6438F–ATARM–21-Jun-10
Node Action
In function of the identifier, the node is concerned, or not, by the LIN response. Consequently,
after sending or receiving the identifier, the USART must be configured. There are three possi-
ble configurations:
This configuration is made by the field, Node Action (NACT), in the US_LINMR register (see
Section
Example: a LIN cluster that contains a Master and two Slaves:
• PUBLISH: the node sends the response.
• SUBSCRIBE: the node receives the response.
• IGNORE: the node is not concerned by the response, it does not send and does not receive
• Data transfer from the Master to the Slave 1 and to the Slave 2:
• Data transfer from the Master to the Slave 1 only:
• Data transfer from the Slave 1 to the Master:
• Data transfer from the Slave1 to the Slave2:
• Data transfer from the Slave2 to the Master and to the Slave1:
the response.
NACT(Master)=PUBLISH
NACT(Slave1)=SUBSCRIBE
NACT(Slave2)=SUBSCRIBE
NACT(Master)=PUBLISH
NACT(Slave1)=SUBSCRIBE
NACT(Slave2)=IGNORE
NACT(Master)=SUBSCRIBE
NACT(Slave1)=PUBLISH
NACT(Slave2)=IGNORE
NACT(Master)=IGNORE
NACT(Slave1)=PUBLISH
NACT(Slave2)=SUBSCRIBE
NACT(Master)=SUBSCRIBE
NACT(Slave1)=SUBSCRIBE
NACT(Slave2)=PUBLISH
33.8.16).
AT91SAM9G45
604

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