LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 164

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
10.12.15 Receive Status Vector Register (RSV - 0x5000 0160)
purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are
TSV1 register.
Table 161. Transmit Status Vector 1 register (TSV1 - address 0x5000 015C) bit description
The Receive status vector register (RSV) is a read-only register with an address of
0x5000 0160. The receive status vector register stores the most recent receive status
returned by the MAC. This register is provided for debug purposes, because the
communication between driver software and the Ethernet block takes place primarily
through the frame descriptors. The status register contents are valid as long as the
internal status of the MAC is valid and should typically only be read when the transmit and
receive processes are halted.
Table 162
Table 162. Receive Status Vector register (RSV - address 0x5000 0160) bit description
Bit
15:0
19:16 Transmit collision
31:20 -
Bit
15:0
16
17
18
19
20
21
22
23
24
25
Symbol
Transmit byte count
count
Symbol
Received byte count
Packet previously
ignored
RXDV event
previously seen
Carrier event
previously seen
Receive code
violation
CRC error
Length check error
Length out of range
Receive OK
Multicast
Broadcast
lists the bit definitions of the RSV register.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
[1]
The total number of bytes in the frame, not counting the
Indicates the frame length field does not match the actual
The packet destination was a broadcast address.
Function
collided bytes.
Number of collisions the current packet incurred during
transmission attempts. The maximum number of collisions
(16) cannot be represented.
Unused
Function
Indicates length of received frame.
Indicates that a packet was dropped.
Indicates that the last receive event seen was not long
enough to be a valid packet.
Indicates that at some time since the last receive statistics,
a carrier event was detected.
Indicates that received PHY data does not represent a
valid receive code.
The attached CRC in the packet did not match the
internally generated CRC.
number of data items and is not a type field.
Indicates that frame type/length field was larger than
1518 bytes.
The packet had valid CRC and no symbol errors.
The packet destination was a multicast address.
halted.Table 161
lists the bit definitions of the
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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0
Reset
value
0x0
0x0
0x0
Reset
value
0x0
0
0
0
0
0
0
0
0
0