LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 475

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
20.4 Pin descriptions
Table 403. Pin descriptions
UM10360
User manual
Pin Name
I2SRX_CLK
I2SRX_WS
I2SRX_SDA
RX_MCLK
I2STX_CLK
I2STX_WS
I2STX_SDA
TX_MCLK
Fig 100. Simple I
TRANSMITTER
(MASTER)
Input/
Input/
Input/
Input/
Type
Output
Input/
Output
Output
Output
Output
Input/
Output
Output
Output
2
S configurations and bus timing
SCK
WS
SD
SCK: serial clock
WS: word select
SD: serial data
Description
Receive Clock. A clock signal used to synchronize the transfer of data on the receive channel. It is
driven by the master and received by the slave. Corresponds to the signal SCK in the I
specification.
Receive Word Select. Selects the channel from which data is to be received. It is driven by the
master and received by the slave. Corresponds to the signal WS in the I
WS = 0 indicates that data is being received by channel 1 (left channel).
WS = 1 indicates that data is being received by channel 2 (right channel).
Receive Data. Serial data, received MSB first. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I
Optional master clock output for the
Transmit Clock. A clock signal used to synchronize the transfer of data on the transmit channel. It
is driven by the master and received by the slave. Corresponds to the signal SCK in the I
specification.
Transmit Word Select. Selects the channel to which data is being sent. It is driven by the master
and received by the slave. Corresponds to the signal WS in the I
WS = 0 indicates that data is being sent to channel 1 (left channel).
WS = 1 indicates that data is being sent to channel 2 (right channel).
Transmit Data. Serial data, sent MSB first. It is driven by the transmitter and read by the receiver.
Corresponds to the signal SD in the I
Optional master clock output for the
right channel
word n-1
TRANSMITTER
RECEIVER
(SLAVE)
All information provided in this document is subject to legal disclaimers.
(SLAVE)
MSB
Rev. 2 — 19 August 2010
CONTROLLER
(MASTER)
SCK
WS
SD
I
I
2
2
2
S bus specification.
S
S
left channel
receive function.
transmit function.
word n
2
RECEIVER
S bus specification.
TRANSMITTER
(SLAVE)
(SLAVE)
LSB
SCK: serial clock
WS: word select
SD: serial data
2
S bus specification.
MSB
right channel
word n+1
Chapter 20: LPC17xx I2S
2
S bus specification.
UM10360
© NXP B.V. 2010. All rights reserved.
RECEIVER
(MASTER)
2
S bus
2
475 of 840
S bus