LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 500

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
21.8 Architecture
UM10360
User manual
The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure
Fig 116. Timer block diagram
116.
MAT[3:0]
INTERRUPT
CAP[3:0]
DMA REQUEST[1:0]
DMA CLEAR[1:0]
STOP ON MATCH
RESET ON MATCH
LOAD[3:0]
All information provided in this document is subject to legal disclaimers.
CAPTURE CONTROL REGISTER
EXTERNAL MATCH REGISTER
MATCH CONTROL REGISTER
INTERRUPT REGISTER
TIMER CONTROL REGISTER
CAPTURE REGISTER 0
CAPTURE REGISTER 1
MATCH REGISTER 0
MATCH REGISTER 1
MATCH REGISTER 2
MATCH REGISTER 3
Rev. 2 — 19 August 2010
RESERVED
RESERVED
CONTROL
reset
enable
CSN
Chapter 21: LPC17xx Timer 0/1/2/3
MAXVAL
=
PRESCALE REGISTER
PRESCALE COUNTER
TIMER COUNTER
=
=
CE
UM10360
TCI
© NXP B.V. 2010. All rights reserved.
=
PCLK
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