LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 774

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.4.3.9 System Handler Priority Registers
Table 662. CCR bit assignments
The SHPR1-SHPR3 registers set the priority level, 0 to 31 of the exception handlers that
have configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in
attributes.
The system fault handlers and the priority field and register for each handler are:
Bits
[31:10]
[9]
[8]
[7:5]
[4]
[3]
[2]
[1]
[0]
Name
-
STKALIGN
BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data bus faults caused
-
DIV_0_TRP
UNALIGN_T
RP
-
USERSETM
PEND
NONEBASE
THRDENA
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Function
Reserved.
Indicates stack alignment on exception entry:
0 = 4-byte aligned
1 = 8-byte aligned.
On exception entry, the processor uses bit[9] of the stacked PSR to
indicate the stack alignment. On return from the exception it uses this
stacked bit to restore the correct stack alignment.
by load and store instructions. This applies to the hard fault, NMI, and
FAULTMASK escalated handlers:
0 = data bus faults caused by load and store instructions cause a lock-up
1 = handlers running at priority -1 and -2 ignore data bus faults caused
by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
Reserved.
Enables faulting or halting when the processor executes an SDIV or UDIV
instruction with a divisor of 0:
0 = do not trap divide by 0
1 = trap divide by 0.
When this bit is set to 0,a divide by zero returns a quotient of 0.
Enables unaligned access traps:
0 = do not trap unaligned halfword and word accesses
1 = trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM , STM , LDRD , and STRD instructions always fault irrespective
of whether UNALIGN_TRP is set to 1.
Reserved.
Enables unprivileged software access to the STIR, see
0 = disable
1 = enable.
Indicates how the processor enters Thread mode:
0 = processor can enter Thread mode only when no exception is active.
1 = processor can enter Thread mode from any level under the control of
an EXC_RETURN value, see
Chapter 34: Appendix: Cortex-M3 user guide
Section 34.3.3.7.2 “Exception
Table 654
UM10360
© NXP B.V. 2010. All rights reserved.
Table
for their
return”.
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