LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 372
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
16.9 Centralized CAN registers
Table 337. Central Transit Status Register (CANTxSR - address 0x4004 0000) bit description
Table 338. Central Receive Status Register (CANRxSR - address 0x4004 0004) bit description
UM10360
User manual
16
17:16 TCS2
31:18 -
Bit
0
1
7:2
8
9
15:10 -
Bit
0
1
7:2
8
9
15:10 -
16
17:16 DOS2
31:18 -
Symbol
TS1
TS2
-
TBS1
TBS2
TCS1
Symbol
RS1
RS2
-
RB1
RB2
DOS1
16.9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000)
16.9.2 Central Receive Status Register (CANRxSR - 0x4004 0004)
Description
When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).
When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in
CAN1GSR).
When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in
CAN2GSR).
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When 1, all requested transmissions have been completed successfully by the CAN1
controller (same as TCS in CAN1GSR).
When 1, all requested transmissions have been completed successfully by the CAN2
controller (same as TCS in CAN2GSR).
Reserved, the value read from a reserved bit is not defined.
Description
When 1, CAN1 is receiving a message (same as RS in CAN1GSR).
When 1, CAN2 is receiving a message (same as RS in CAN2GSR).
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When 1, a received message is available in the CAN1 controller (same as RBS in
CAN1GSR).
When 1, a received message is available in the CAN2 controller (same as RBS in
CAN2GSR).
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When 1, a message was lost because the preceding message to CAN1 controller was not
read out quickly enough (same as DOS in CAN1GSR).
When 1, a message was lost because the preceding message to CAN2 controller was not
read out quickly enough (same as DOS in CAN2GSR).
Reserved, the value read from a reserved bit is not defined.
For easy and fast access, all CAN Controller Status bits from each CAN Controller Status
register are bundled together. Each defined byte of the following registers contains one
particular status bit from each of the CAN controllers, in its LS bits.
All Status registers are read-only and allow byte, half word and word access.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
NA
Reset Value
0
0
NA
1
1
NA
1
1
NA
Reset Value
0
0
NA
0
0
NA
0
0
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