LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 821

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
10.12.7
10.12.8
10.12.9
10.12.10 Transmit Number of Descriptors Register
10.12.11 Transmit Produce Index Register
10.12.12 Transmit Consume Index Register
10.12.13 Transmit Status Vector 0 Register (TSV0 -
10.12.14 Transmit Status Vector 1 Register (TSV1 -
10.12.15 Receive Status Vector Register (RSV -
10.12.16 Flow Control Counter Register
10.12.17 Flow Control Status Register (FlowControlStatus -
10.13
10.13.1
10.13.2
10.13.3
10.13.4
10.13.5
10.14
10.14.1
10.14.2
Chapter 11: LPC17xx USB device controller
11.1
11.2
11.3
11.4
11.5
11.6
11.6.1
11.6.2
UM10360
User manual
Receive filter register definitions . . . . . . . . . 166
Module control register definitions . . . . . . . 168
How to read this chapter . . . . . . . . . . . . . . . . 213
Basic configuration . . . . . . . . . . . . . . . . . . . . 213
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Fixed endpoint configuration . . . . . . . . . . . . 214
Functional description . . . . . . . . . . . . . . . . . 215
Receive Consume Index Register
(RxConsumeIndex - 0x5000 0118) . . . . . . . . 160
Transmit Descriptor Base Address Register
(TxDescriptor - 0x5000 011C). . . . . . . . . . . . 161
Transmit Status Base Address Register (TxStatus
- 0x5000 0120) . . . . . . . . . . . . . . . . . . . . . . . 161
(TxDescriptorNumber - 0x5000 0124) . . . . . 161
(TxProduceIndex - 0x5000 0128) . . . . . . . . . 162
(TxConsumeIndex - 0x5000 012C). . . . . . . . 162
0x5000 0158) . . . . . . . . . . . . . . . . . . . . . . . . 162
0x5000 015C) . . . . . . . . . . . . . . . . . . . . . . . . 163
0x5000 0160) . . . . . . . . . . . . . . . . . . . . . . . . 164
(FlowControlCounter - 0x5000 0170) . . . . . . 165
0x5000 0174) . . . . . . . . . . . . . . . . . . . . . . . . 165
Receive Filter Control Register (RxFilterCtrl -
0x5000 0200) . . . . . . . . . . . . . . . . . . . . . . . . 166
Receive Filter WoL Status Register
(RxFilterWoLStatus - 0x5000 0204) . . . . . . . 166
Receive Filter WoL Clear Register
(RxFilterWoLClear - 0x5000 0208) . . . . . . . . 167
Hash Filter Table LSBs Register (HashFilterL -
0x5000 0210) . . . . . . . . . . . . . . . . . . . . . . . . 167
Hash Filter Table MSBs Register (HashFilterH -
0x5000 0214) . . . . . . . . . . . . . . . . . . . . . . . . 168
Interrupt Status Register (IntStatus -
0x5000 0FE0) . . . . . . . . . . . . . . . . . . . . . . . . 168
Interrupt Enable Register (IntEnable -
0x5000 0FE4) . . . . . . . . . . . . . . . . . . . . . . . . 169
Analog transceiver . . . . . . . . . . . . . . . . . . . . 216
Serial Interface Engine (SIE) . . . . . . . . . . . . 216
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
10.14.3
10.14.4
10.14.5
10.15
10.15.1
10.15.2
10.16
10.16.1
10.16.2
10.17
10.17.1
10.17.2
10.17.3
10.17.4
10.17.5
10.17.6
10.17.7
10.17.8
10.17.9
10.17.10 Receive filtering . . . . . . . . . . . . . . . . . . . . . . 198
10.17.11 Power management. . . . . . . . . . . . . . . . . . . 200
10.17.12 Wake-up on LAN . . . . . . . . . . . . . . . . . . . . . 200
10.17.13 Enabling and disabling receive and transmit 202
10.17.14 Transmission padding and CRC . . . . . . . . . 204
10.17.15 Huge frames and frame length checking . . . 205
10.17.16 Statistics counters . . . . . . . . . . . . . . . . . . . . 205
10.17.17 MAC status vectors . . . . . . . . . . . . . . . . . . . 205
10.17.18 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
10.17.19 Ethernet errors . . . . . . . . . . . . . . . . . . . . . . . 207
10.18
10.18.1
10.18.2
10.18.3
10.19
11.6.3
11.6.4
11.6.5
11.6.6
11.6.7
11.6.8
11.7
11.8
11.9
Descriptor and status formats . . . . . . . . . . . 172
Ethernet block functional description. . . . . 177
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
AHB bandwidth . . . . . . . . . . . . . . . . . . . . . . . 208
CRC calculation. . . . . . . . . . . . . . . . . . . . . . . . 211
Operational overview . . . . . . . . . . . . . . . . . . 217
Pin description . . . . . . . . . . . . . . . . . . . . . . . 218
Clocking and power management. . . . . . . . 218
Interrupt Clear Register (IntClear - 0x5000
0FE8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Interrupt Set Register (IntSet - 0x5000
0FEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Power-Down Register (PowerDown -
0x5000 0FF4). . . . . . . . . . . . . . . . . . . . . . . . 171
Receive descriptors and statuses . . . . . . . . 172
Transmit descriptors and statuses . . . . . . . . 175
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
AHB interface. . . . . . . . . . . . . . . . . . . . . . . . 178
Direct Memory Access (DMA) . . . . . . . . . . . 178
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 181
Transmit process . . . . . . . . . . . . . . . . . . . . . 182
Receive process . . . . . . . . . . . . . . . . . . . . . 188
Transmission retry . . . . . . . . . . . . . . . . . . . . 194
Status hash CRC calculations . . . . . . . . . . . 194
Duplex modes . . . . . . . . . . . . . . . . . . . . . . . 195
IEE 802.3/Clause 31 flow control. . . . . . . . . 195
Half-Duplex mode backpressure . . . . . . . . . 197
DMA access. . . . . . . . . . . . . . . . . . . . . . . . . 208
Types of CPU access. . . . . . . . . . . . . . . . . . 209
Overall bandwidth . . . . . . . . . . . . . . . . . . . . 209
Endpoint RAM (EP_RAM) . . . . . . . . . . . . . . 216
EP_RAM access control . . . . . . . . . . . . . . . 216
DMA engine and bus master interface. . . . . 217
Register interface. . . . . . . . . . . . . . . . . . . . . 217
SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . 217
GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Chapter 35: Supplementary information
UM10360
© NXP B.V. 2010. All rights reserved.
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