LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 662

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
34.2.4.2.1 Syntax
34.2.4.2.2 Operation
34.2.4.2 LDR and STR, immediate offset
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed
immediate offset.
op{type}{cond} Rt, [Rn {, #offset}]
op{type}{cond} Rt, [Rn, #offset]!
op{type}{cond} Rt, [Rn], #offset
opD{cond} Rt, Rt2, [Rn {, #offset}]
opD{cond} Rt, Rt2, [Rn, #offset]!
opD{cond} Rt, Rt2, [Rn], #offset
where:
op is one of:
type is one of:
cond is an optional condition code, see
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an offset from Rn. If offset is omitted, the address is the contents of Rn.
Rt2 is the additional register to load or store for two-word operations.
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing
modes:
•
LDR: Load register.
STR: Store register.
B: unsigned byte, zero extend to 32 bits on loads.
SB: signed byte, sign extend to 32 bits (LDR only).
H: unsigned halfword, zero extend to 32 bits on loads.
SH: signed halfword, sign extend to 32 bits (LDR only).
—: omit, for word.
Offset addressing
The offset value is added to or subtracted from the address obtained from the register
Rn. The result is used as the address for the memory access. The register Rn is
unaltered. The assembly language syntax for this mode is:
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
; pre-indexed
; post-indexed
; immediate offset
; pre-indexed, two words
; post-indexed, two words
; immediate offset, two words
Section 34.2.3.7 “Conditional
Chapter 34: Appendix: Cortex-M3 user guide
execution”.
UM10360
© NXP B.V. 2010. All rights reserved.
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