LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 186

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Fig 21. Transmit example memory and registers
0x200810EC
0x200810EC
0x200810FC
0x200810F0
0x200810F4
0x200810F8
0x20081108
TxDescriptor
0x20081100
0x20081104
0 0
0 0
1 1
0 0
descriptor array
0x20081314
0x20081411
0x20081419
0x20081324
CONTROL
Control
CONTROL
CONTROL
CONTROL
Control
Control
Control
Packet
Packet
Packet
Packet
All of the above interrupts can be enabled and disabled by setting or resetting the
corresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
NVIC).
The interrupts, either of individual frames or of the whole list, are a good means of
communication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
Transmit example
Figure 21
of 8 bytes and a frame payload of 12 bytes.
After reset the values of the DMA registers will be zero. During initialization the device
driver will allocate the descriptor and status array in memory. In this example, an array of
four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address
•
In the case of a transmission error (LateCollision, ExcessiveCollision, or
ExcessiveDefer) or a multi-fragment frame where the device driver did provide the
initial fragments but did not provide the rest of the fragments (NoDescriptor) or in the
case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus
register.
7
7
7
3
illustrates the transmit process in an example transmitting uses a frame header
All information provided in this document is subject to legal disclaimers.
PACKET 1 HEADER (8 bytes)
PACKET 0 HEADER (8 bytes)
PACKET 0 PAYLOAD (12 bytes)
fragment buffers
Rev. 2 — 19 August 2010
TxDescriptorNumber
TxConsumeIndex
TxProduceIndex
= 3
0x200811F8
TxStatus
Chapter 10: LPC17xx Ethernet
StatusInfo
StatusInfo
StatusInfo
StatusInfo
status array
UM10360
© NXP B.V. 2010. All rights reserved.
0x200811F8
0x200811FC
0x20081200
0x20081204
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