LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 605
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 564. DMA Channel Configuration registers (DMACCxConfig - 0x5000 41x0)
UM10360
User manual
Bit
0
5:1
10:6
13:11
14
15
16
17
18
31:19
Name
E
SrcPeripheral
DestPeripheral
TransferType
IE
A
H
Reserved
ITC
L
Function
Channel enable. Reading this bit indicates whether a channel is currently enabled or
disabled:
0 = channel disabled.
1 = channel enabled.
The Channel Enable bit status can also be found by reading the DMACEnbldChns
Register.
A channel is enabled by setting this bit.
A channel can be disabled by clearing the Enable bit. This causes the current AHB
transfer (if one is in progress) to complete and the channel is then disabled. Any data
in the FIFO of the relevant channel is lost. Restarting the channel by setting the
Channel Enable bit has unpredictable effects, the channel must be fully re-initialized.
The channel is also disabled, and Channel Enable bit cleared, when the last LLI is
reached, the DMA transfer is completed, or if a channel error is encountered.
If a channel must be disabled without losing data in the FIFO, the Halt bit must be set
so that further DMA requests are ignored. The Active bit must then be polled until it
reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable
bit can be cleared.
Source peripheral. This value selects the DMA source request peripheral. This field is
ignored if the source of the transfer is from memory. See
identification.
Destination peripheral. This value selects the DMA destination request peripheral.
This field is ignored if the destination of the transfer is to memory. See
peripheral identification.
This value indicates the type of transfer. The transfer type can be
memory-to-memory, memory-to-peripheral, peripheral-to-memory, or
peripheral-to-peripheral.
Refer to
Interrupt error mask. When cleared, this bit masks out the error interrupt of the
relevant channel.
Terminal count interrupt mask. When cleared, this bit masks out the terminal count
interrupt of the relevant channel.
Lock. When set, this bit enables locked transfers. This information is not used in the
LPC17xx.
Active:
0 = there is no data in the FIFO of the channel.
1 = the channel FIFO has data.
This value can be used with the Halt and Channel Enable bits to cleanly disable a
DMA channel. This is a read-only bit.
Halt:
0 = enable DMA requests.
1 = ignore further source DMA requests.
The contents of the channel FIFO are drained.
This value can be used with the Active and Channel Enable bits to cleanly disable a
DMA channel.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Table 565
Rev. 2 — 19 August 2010
for the encoding of this field.
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Table 543
UM10360
© NXP B.V. 2010. All rights reserved.
for peripheral
Table 543
605 of 840
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