LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 49
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
4.6.3 PLL1 Configuration register (PLL1CFG - 0x400F C0A4)
4.6.4 PLL1 Status register (PLL1STAT - 0x400F C0A8)
Table 30.
PLL1 must be set up, enabled, and lock established before it may be used as a clock
source for the USB subsystem. The hardware does not insure that the PLL is locked
before it is connected nor does it automatically disconnect the PLL if lock is lost during
operation.
The PLL1CFG register contains the PLL1 multiplier and divider values. Changes to the
PLL1CFG register do not take effect until a correct PLL1 feed sequence has been given
(see
are found in
Table 31.
The read-only PLL1STAT register provides the actual PLL1 parameters that are in effect
at the time it is read, as well as the PLL1 status. PLL1STAT may disagree with values
found in PLL1CON and PLL1CFG because changes to those registers do not take effect
until a proper PLL1 feed has occurred (see
- 0x400F
Bit
0
1
31:2
Bit
4:0
6:5
31:7
Section
Symbol
PLLE1
PLLC1
-
Symbol
MSEL1
PSEL1
-
C0AC)”).
PLL1 Control register (PLL1CON - address 0x400F C0A0) bit description
PLL Configuration register (PLL1CFG - address 0x400F C0A4) bit description
Section
4.6.6). Calculations for the PLL1 frequency, and multiplier and divider values
All information provided in this document is subject to legal disclaimers.
Description
PLL1 Enable. When one, and after a valid PLL1 feed, this bit will
activate PLL1 and allow it to lock to the requested frequency. See
PLL1STAT register,
PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and
locked, then followed by a valid PLL1 feed sequence causes PLL1 to
become the clock source for the USB subsystem via the USB clock
divider. See PLL1STAT register,
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
PLL1 Multiplier value. Supplies the value "M" in the PLL1 frequency
calculations.
Note: For details on selecting the right value for MSEL1 see
Section
PLL1 Divider value. Supplies the value "P" in the PLL1 frequency
calculations.
Note: For details on selecting the right value for PSEL1 see
Section
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
4.6.9.
Rev. 2 — 19 August 2010
4.6.8.
4.6.8.
Table
Chapter 4: LPC17xx Clocking and power control
32.
Section 4.6.6 “PLL1 Feed register (PLL1FEED
Table
32.
UM10360
© NXP B.V. 2010. All rights reserved.
49 of 840
Reset
value
0
0
NA
Reset
value
0
0
NA
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