LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 424
LPC1767FBD100,551
Manufacturer Part Number
LPC1767FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.LPC1767FBD100551.pdf
(2 pages)
2.LPC1767FBD100551.pdf
(840 pages)
3.LPC1767FBD100551.pdf
(65 pages)
Specifications of LPC1767FBD100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
100MHz
Connectivity
Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
LPC17
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4967
935289808551
935289808551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1767FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
18.6.4 SSPn Status Register (SSP0SR - 0x4008 800C, SSP1SR -
18.6.5 SSPn Clock Prescale Register (SSP0CPSR - 0x4008 8010, SSP1CPSR
18.6.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0x4008 8014,
0x4003 000C)
This read-only register reflects the current status of the SSP controller.
Table 373: SSPn Status Register (SSP0SR - address 0x4008 800C, SSP1SR - 0x4003 000C)
- 0x4003 0010)
This register controls the factor by which the Prescaler divides the SSP peripheral clock
SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in
SSPnCR0, to determine the bit clock.
Table 374: SSPn Clock Prescale Register (SSP0CPSR - address 0x4008 8010, SSP1CPSR -
Important: the SSPnCPSR value must be properly initialized or the SSP controller will not
be able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock selected in
not relevant.
In master mode, CPSDVSR
SSP1IMSC - 0x4003 0014)
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Bit
0
1
2
3
4
31:5
Bit
7:0
31:8
Symbol
CPSDVSR
-
Symbol Description
TFE
TNF
RNE
RFF
BSY
-
bit description
0x4003 0010) bit description
All information provided in this document is subject to legal disclaimers.
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if
not.
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently
sending/receiving a frame and/or the Tx FIFO is not empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
This even value between 2 and 254, by which SSP_PCLK is divided
to yield the prescaler output clock. Bit 0 always reads as 0.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
min
= 2 or larger (even numbers only).
Section
4.7.3. The content of the SSPnCPSR register is
Chapter 18: LPC17xx SSP0/1
UM10360
© NXP B.V. 2010. All rights reserved.
424 of 840
Reset
Value
1
0
0
NA
Reset
Value
0
NA
0
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