LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 345

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
UM10360
User manual
Fig 53. CAN controller block diagram
ACCEPTANCE
16.5.1 APB Interface Block (AIB)
16.5.2 Interface Management Logic (IML)
16.5.3 Transmit Buffers (TXB)
REGISTER
COMMON
APB BUS
STATUS
FILTER
NVIC
The APB Interface Block provides access to all CAN Controller registers.
The Interface Management Logic interprets commands from the CPU, controls internal
addressing of the CAN Registers and provides interrupts and status information to the
CPU.
The TXB represents a Triple Transmit Buffer, which is the interface between the Interface
Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is
able to store a complete message which can be transmitted over the CAN network. This
buffer is written by the CPU and read out by the BSP.
•
•
•
Nested Vectored Interrupt Controller (NVIC)
CAN Transceiver
Common Status Registers
MANAGEMENT
BUFFERS 1,2
BUFFERS 1
INTERFACE
TRANSMIT
RECEIVE
LOGIC
AND 3
AND 2
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
MANAGEMENT
PROCESSOR
CAN CORE
STREAM
ERROR
BLOCK
TIMING
LOGIC
LOGIC
BIT
BIT
TX
RX
Chapter 16: LPC17xx CAN1/2
TRANSCEIVER
CAN
UM10360
© NXP B.V. 2010. All rights reserved.
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