LPC1767FBD100,551 NXP Semiconductors, LPC1767FBD100,551 Datasheet - Page 648

• Manufacturer Part Number: LPC1767FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1767FBD100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC17
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4967; 935289808551

NXP Semiconductors
Table 612. Cortex-M3 instructions
UM10360
User manual
Mnemonic
ISB
IT
LDM
LDMDB, LDMEA
LDMFD, LDMIA
LDR
LDRB, LDRBT
LDRD
LDREX
LDREXB
LDREXH
LDRH, LDRHT
LDRSB, LDRSBT
LDRSH, LDRSHT
LDRT
LSL, LSLS
LSR, LSRS
MLA
MLS
MOV, MOVS
MOVT
MOVW, MOV
MRS
MSR
MUL, MULS
MVN, MVNS
NOP
ORN, ORNS
ORR, ORRS
POP
PUSH
RBIT
REV
REV16
REVSH
ROR, RORS
RRX, RRXS
RSB, RSBS
SBC, SBCS
SBFX
Operands
-
-
Rn{!}, reglist
Rn{!}, reglist
Rn{!}, reglist
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, Rt2, [Rn, #offset] Load Register with two bytes
Rt, [Rn, #offset]
Rt, [Rn]
Rt, [Rn]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rd, Rm, <Rs|#n>
Rd, Rm, <Rs|#n>
Rd, Rn, Rm, Ra
Rd, Rn, Rm, Ra
Rd, Op2
Rd, #imm16
Rd, #imm16
Rd, spec_reg
spec_reg, Rm
{Rd,} Rn, Rm
Rd, Op2
-
{Rd,} Rn, Op2
{Rd,} Rn, Op2
reglist
reglist
Rd, Rn
Rd, Rn
Rd, Rn
Rd, Rn
Rd, Rm, <Rs|#n>
Rd, Rm
{Rd,} Rn, Op2
{Rd,} Rn, Op2
Rd, Rn, #lsb, #width
…continued
All information provided in this document is subject to legal disclaimers.
Brief description
Instruction Synchronization Barrier
If-Then condition block
Load Multiple registers, increment after
Load Multiple registers, decrement before
Load Multiple registers, increment after
Load Register with word
Load Register with byte
Load Register Exclusive
Load Register Exclusive with byte
Load Register Exclusive with halfword
Load Register with halfword
Load Register with signed byte
Load Register with signed halfword
Load Register with word
Logical Shift Left
Logical Shift Right
Multiply with Accumulate, 32-bit result
Multiply and Subtract, 32-bit result
Move
Move Top
Move 16-bit constant
Move from special register to general register
Move from general register to special register
Multiply, 32-bit result
Move NOT
No Operation
Logical OR NOT
Logical OR
Pop registers from stack
Push registers onto stack
Reverse Bits
Reverse byte order in a word
Reverse byte order in each halfword
Reverse byte order in bottom halfword and sign
extend
Rotate Right
Rotate Right with Extend
Reverse Subtract
Subtract with Carry
Signed Bit Field Extract
Rev. 2 — 19 August 2010
Chapter 34: Appendix: Cortex-M3 user guide
Flags
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N,Z,C
N,Z,C
-
-
N,Z,C
-
N,Z,C
-
N,Z,C,V
N,Z
N,Z,C
-
N,Z,C
N,Z,C
-
-
-
-
-
-
N,Z,C
N,Z,C
N,Z,C,V
N,Z,C,V
-
UM10360
© NXP B.V. 2010. All rights reserved.
Page
Section 34.2.10.5
Section 34.2.9.3
Section 34.2.4.6
Section 34.2.4.6
Section 34.2.4.6
Section 34.2.4
Section 34.2.4
Section 34.2.4.2
Section 34.2.4.8
Section 34.2.4.8
Section 34.2.4.8
Section 34.2.4
Section 34.2.4
Section 34.2.4
Section 34.2.4
Section 34.2.5.3
Section 34.2.5.3
Section 34.2.6.1
Section 34.2.6.1
Section 34.2.5.6
Section 34.2.5.7
Section 34.2.5.6
Section 34.2.10.6
Section 34.2.10.7
Section 34.2.6.1
Section 34.2.5.6
Section 34.2.10.8
Section 34.2.5.2
Section 34.2.5.2
Section 34.2.4.7
Section 34.2.4.7
Section 34.2.5.8
Section 34.2.5.8
Section 34.2.5.8
Section 34.2.5.8
Section 34.2.5.3
Section 34.2.5.3
Section 34.2.5.1
Section 34.2.5.1
Section 34.2.8.2
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